Technical Field
The present invention relates in general to a system clock supplying circuit, particularly, to a phase compensation circuit of a digital processing phase-locked loop(hereinafter, referred to DPPLL) capable of hitless switching such that a phase is not changed during switching a system clock, by matching the phase perfectly as well as frequency compensation in the DPPLL.
Additionally, the present invention relates to the phase compensation circuit of the DPPLL capable of hitless switching by matching the phase perfectly as well as frequency compensation generated from a pair of clock units in a clock supplying system in case that a phase is changed because a reference clock inputted to each clock unit includes jitter or in case that there is no input reference clock, in which the clock supplying system consists of main and reserved units for supplying the clock by duplicating the pair of clock units respectively.